<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>CMOS | Lin's Lab</title><link>https://www.linqiuyang.com/en/tag/cmos/</link><atom:link href="https://www.linqiuyang.com/en/tag/cmos/index.xml" rel="self" type="application/rss+xml"/><description>CMOS</description><generator>Hugo Blox Builder (https://hugoblox.com)</generator><language>en</language><lastBuildDate>Mon, 24 Aug 2026 00:00:00 +0000</lastBuildDate><image><url>https://www.linqiuyang.com/media/icon_hu17276893506282036950.png</url><title>CMOS</title><link>https://www.linqiuyang.com/en/tag/cmos/</link></image><item><title>Review: A Highly-Integrated 1536-Channel Quad-Shank Monolithic Neural Probe in 55nm CMOS for Full-Band Raw-Signal Recording</title><link>https://www.linqiuyang.com/en/research/review/neural-interface-ics/1536-channel-quad-shank-neural-probe/</link><pubDate>Mon, 24 Aug 2026 00:00:00 +0000</pubDate><guid>https://www.linqiuyang.com/en/research/review/neural-interface-ics/1536-channel-quad-shank-neural-probe/</guid><description>&lt;h2 id="paper">Paper&lt;/h2>
&lt;p>&lt;strong>A Highly-Integrated 1536-Channel Quad-Shank Monolithic Neural Probe in 55nm CMOS for Full-Band Raw-Signal Recording&lt;/strong>&lt;/p>
&lt;p>&lt;strong>Review by:&lt;/strong> 王奕如&lt;/p>
&lt;p>&lt;strong>Full Review:&lt;/strong> &lt;a href="https://www.linqiuyang.com/research/review/neural-interface-ics/1536-channel-quad-shank-neural-probe/paper.pdf">View Review Document (PDF)&lt;/a>&lt;/p>
&lt;hr>
&lt;h2 id="overview">Overview&lt;/h2>
&lt;p>This work presents a &lt;strong>1536-channel quad-shank monolithic neural probe&lt;/strong> fabricated in 55 nm CMOS, supporting simultaneous recording from up to &lt;strong>1536 out of 5120 electrodes&lt;/strong>.&lt;/p>
&lt;p>Rather than focusing solely on minimum area or power per channel, the work addresses system-level trade-offs in large-scale neural recording, including &lt;strong>electrode density, noise, power, area, multiplexing, and data readout&lt;/strong>.&lt;/p>
&lt;hr>
&lt;h2 id="key-features">Key Features&lt;/h2>
&lt;ul>
&lt;li>&lt;strong>5120 electrodes / 1536 simultaneous recording channels&lt;/strong>&lt;/li>
&lt;li>Conventional &lt;strong>IA–buffer–MUX–SAR ADC&lt;/strong> signal chain&lt;/li>
&lt;li>Dynamically biased buffers for reduced power&lt;/li>
&lt;li>96 shared &lt;strong>12-bit SAR ADCs&lt;/strong>&lt;/li>
&lt;li>Shared ADC reference buffers&lt;/li>
&lt;li>Full-band recording of both AP and LFP signals&lt;/li>
&lt;/ul>
&lt;hr>
&lt;h2 id="key-results">Key Results&lt;/h2>
&lt;table>
&lt;thead>
&lt;tr>
&lt;th style="text-align: left">Parameter&lt;/th>
&lt;th style="text-align: right">Performance&lt;/th>
&lt;/tr>
&lt;/thead>
&lt;tbody>
&lt;tr>
&lt;td style="text-align: left">Technology&lt;/td>
&lt;td style="text-align: right">55 nm CMOS&lt;/td>
&lt;/tr>
&lt;tr>
&lt;td style="text-align: left">Recording Electrodes&lt;/td>
&lt;td style="text-align: right">5120&lt;/td>
&lt;/tr>
&lt;tr>
&lt;td style="text-align: left">Simultaneous Recording Channels&lt;/td>
&lt;td style="text-align: right">1536&lt;/td>
&lt;/tr>
&lt;tr>
&lt;td style="text-align: left">Probe Structure&lt;/td>
&lt;td style="text-align: right">Quad-shank&lt;/td>
&lt;/tr>
&lt;tr>
&lt;td style="text-align: left">ADC&lt;/td>
&lt;td style="text-align: right">12-bit SAR&lt;/td>
&lt;/tr>
&lt;tr>
&lt;td style="text-align: left">Channel Area&lt;/td>
&lt;td style="text-align: right">0.012 mm²/ch&lt;/td>
&lt;/tr>
&lt;tr>
&lt;td style="text-align: left">Total Power&lt;/td>
&lt;td style="text-align: right">29.7 mW&lt;/td>
&lt;/tr>
&lt;tr>
&lt;td style="text-align: left">Power / Channel&lt;/td>
&lt;td style="text-align: right">19.34 µW/ch&lt;/td>
&lt;/tr>
&lt;tr>
&lt;td style="text-align: left">AP Input-Referred Noise&lt;/td>
&lt;td style="text-align: right">6.01 ± 0.39 µVrms&lt;/td>
&lt;/tr>
&lt;tr>
&lt;td style="text-align: left">LFP Input-Referred Noise&lt;/td>
&lt;td style="text-align: right">7.58 ± 0.79 µVrms&lt;/td>
&lt;/tr>
&lt;tr>
&lt;td style="text-align: left">ADC SNDR&lt;/td>
&lt;td style="text-align: right">64.92 dB&lt;/td>
&lt;/tr>
&lt;/tbody>
&lt;/table>
&lt;hr>
&lt;h2 id="takeaway">Takeaway&lt;/h2>
&lt;p>This work provides a representative example of &lt;strong>system-level optimization for high-density neural recording&lt;/strong>, balancing channel density, noise, power, area, and system scalability.&lt;/p>
&lt;p>It also demonstrates that the conventional &lt;strong>IA + MUX + SAR ADC&lt;/strong> architecture remains highly competitive for large-scale neural recording when carefully optimized.&lt;/p>
&lt;p>For detailed discussions of the pixel architecture, instrumentation amplifier, dynamic-bias buffer, SAR ADC, and reference buffer design, please refer to the &lt;strong>&lt;a href="https://www.linqiuyang.com/research/review/neural-interface-ics/1536-channel-quad-shank-neural-probe/paper.pdf">full review document&lt;/a>&lt;/strong>.&lt;/p></description></item></channel></rss>